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HANBit
HMD32M32M16G
128Mbyte (32Mx32) 72-pin Fast Page Mode 4K Ref. SIMM Design 5V Part No. HMD32M32M16G
GENERAL DESCRIPTION
The HMD32M32M16G is a 32M x 32bit dynamic RAM high-density memory module. The module consists of sixteen CMOS 16M x 4bit DRAMs in 32-pin TSOPII packages mounted on a 72-pin, double-sided, FR-4-printed circuit board. A 0.1uF decoupling capacitor is mounted on the printed circuit board for each DRAM components. The module is a Single In-line Memory Module with edge connections and is intended for mounting in to 72-pin edge connector sockets. All module components may be powered from a single 5V DC power supply and all inputs and outputs are TTL-compatible.
FEATURES
wPart Identification HMD32M32M16G-- 4K Cycles/64ms Ref. Gold w Access times : 50, 60ns w High-density 128MByte design w Single + 5V 0.5V power supply w JEDEC standard pinout w Fast Page mode operation w TTL compatible inputs and outputs w FR4-PCB design PIN 1 2 3 4 5 6 7 8 9 Vss DQ0
PIN ASSIGNMENT
SYMBOL PIN 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 SYMBOL DQ22 DQ7 DQ23 A7 A11 Vcc A8 A9 /RAS3 /RAS2 NC NC NC NC Vss /CAS0 /CAS2 /CAS3 /CAS1 /RAS0 /RAS1 NC /WE NC PIN 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 SYMBOL DQ8 DQ24 DQ9 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 Vcc DQ29 DQ13 DQ30 DQ14 DQ31 DQ15 NC PD1 PD2 PD3 PD4 NC Vss
DQ16 DQ1 DQ17 DQ2 DQ18 DQ3 DQ19 Vcc NC A0 A1 A2 A3 A4 A5 A6 A10 DQ4 DQ20 DQ5 DQ21 DQ6
OPTIONS
w Timing 50ns access 60ns access w Packages 72-pin SIMM
MARKING
-5 -6 M
10 11 12 13 14 15 16 17 tRC 90ns 110ns 18 19 20 21 22 23
PERFORMANCE RANGE
SPEED -5 -6 tRAC 50ns 60ns tCAC 13ns 15ns
PRESENCE DETECT PINS
Pin PD1 PD2 PD3 PD4 50ns NC Vss Vss Vss 60ns NC Vss NC NC
24
72 PIN
SIMM TOP VIEW
URL:www.hbe.co.kr REV.1.0 (August.2002)
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FUNCTIONAL BLOCK DIAGRAM
/CAS0 /RAS0 /CAS /RAS /OE DQ1 DQ2 DQ3 DQ4 DQ4-DQ7 DQ0-DQ3 DQ1 DQ2 DQ3 DQ4
HMD32M32M16G
U1
U5
/WE
/CAS /RAS /OE A0-A11
/CAS0 /RAS1
/WE A0 -A11
/CAS /RAS /OE /WE
U2
A0 -A11
DQ1 DQ2 DQ3 DQ4
DQ1 DQ2 DQ3 DQ4
U6
/WE
/CAS /RAS /OE A0 -A11
/CAS1
/CAS /RAS /OE /WE
U3 A0 -A11
DQ1 DQ2 DQ3 DQ4
DQ8-DQ11 DQ1 DQ2 DQ3 DQ4
U7
/WE
/CAS /RAS /OE A0 -A11
/CAS1
DQ12-DQ15 /CAS /RAS /OE /WE
U4
A0 -A11
DQ1 DQ2 DQ3 DQ4 DQ16-DQ19
DQ1 DQ2 DQ3 DQ4
U8
/WE
/CAS /RAS /OE A0 -A11
/CAS2 /RAS2
/CAS /RAS /OE /WE
U9
A0 -A11
DQ1 DQ2 DQ3 DQ4 DQ20-DQ23
DQ1 DQ2 DQ3 DQ4
U13
/WE
/CAS /RAS /OE A0 -A11
/CAS2 /RAS3
/CAS /RAS /OE /WE
U10
A0 -A11
DQ1 DQ2 DQ3 DQ4 DQ24-DQ27
DQ1 DQ2 DQ3 DQ4
U14
/WE
/CAS /RAS /OE A0 -A11
/CAS3
/CAS /RAS /OE /WE
U11
A0 -A11
DQ1 DQ2 DQ3 DQ4 DQ28-DQ31
DQ1 DQ2 DQ3 DQ4
U15
/WE
/CAS /RAS /OE A0 -A11
/CAS3
/CAS /RAS /OE /WE /WE A0-A11
U12
A0 -A11
DQ1 DQ2 DQ3 DQ4
DQ1 DQ2 DQ3 DQ4
U16
/WE
/CAS /RAS /OE A0 -A11
Vcc Vss
0.1uF Capacitor for each DRAM
To all DRAMs
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ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to Vss Power Dissipation Storage Temperature SYMBOL VIN ,OUT Vcc PD TSTG
HMD32M32M16G
RATING -1V to 7.0V -1V to 7.0V 16W -55oC to 150oC
Short Circuit Output Current IOS 50mA w Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
( Voltage reference to VSS, TA=0 to 70 o C ) PARAMETER Supply Voltage Ground Input High Voltage Input Low Voltage SYMBOL Vcc Vss VIH VIL MIN 4.5 0 2.4 -1.0 TYP. 5.0 0 MAX 5.5 0 Vcc+1 0.8 UNIT V V V V
DC AND OPERATING CHARACTERISTICS
SYMBOL ICC1 -6 ICC2 ICC3 -6 -5 ICC4 -6 ICC5 ICC6 -6 Il(L) IO(L) VOH VOL ICC1 : Operating Current * (/RAS , /CAS , Address cycling @tRC=min.) ICC2 : Standby Current ( /RAS=/CAS=VIH ) ICC3 : /RAS Only Refresh Current * ( /CAS=V IH, /RAS, Address cycling @tRC=min )
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SPEED -5
MIN -10 -5 2.4 -
MAX 1920 1760 32 1920 1760 1120 960 16 1920 1760 10 5 0.4
UNITS mA mA mA mA mA mA mA mA mA mA A A V V
Don't care -5
Don't care -5
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ICC4 : Fast Page Mode Current * (/RAS=VIL, /CAS, Address cycling @tPC=min ) ICC5 : Standby Current (/RAS=/CAS=Vcc-0.2V ) ICC6 : /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t RC=min ) IIL : Input Leakage Current (Any input 0V VIN 6.5V, all other pins not under test = 0V) IOL : Output Leakage Current (Data out is disabled, 0V VOUT 5.5V VOH : Output High Voltage Level (IOH= -5mA ) VOL : Output Low Voltage Level (IOL = 4.2mA )
HMD32M32M16G
* NOTE: ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address cad be changed maximum once while /RAS=VIL. In ICC4, address can be changed maximum once within one page mode cycle.
CAPACITANCE
( TA=25 C, Vcc = 5V, f = 1Mz ) SYMBOL CIN1 C IN2 CIN3 CIN4 CDQ1
o
o
DESCRIPTION Input Capacitance (A0-A11) Input Capacitance (/W) Input Capacitance (/RAS0) Input Capacitance (/CAS0-/CAS3) Input/Output Capacitance (DQ0-31)
MIN -
MAX 90 122 38 38 17
UNITS pF pF pF pF pF
AC CHARACTERISTICS
PARAMETER Random read or write cycle time Access time from /RAS Access time from /CAS Access time from column address /CAS to output in Low-Z Output buffer turn-off delay Transition time (rise and fall) /RAS precharge time /RAS pulse width /RAS hold time /CAS hold time /CAS pulse width /RAS to /CAS delay time
( 0 C TA 70oC , Vcc = 5V10%, See notes 1,2.) -5 SYMBOL MIN tRC tRAC tCAC tAA tCLZ tOFF tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR 3 3 1 30 50 13 38 8 20 15 5 0
-4-
-6 UNIT MIN 104 50 13 25 3 13 50 3 1 40 10K 60 15 45 10K 37 25 10 20 15 5 0 10K 45 30 10K 15 50 60 15 30 MAX ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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MAX
84
/RAS to column address delay time /CAS to /RAS precharge time Row address set-up time
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Row address hold time Column address set-up time Column Address to /RAS lead time Read command set-up time Read command hold referenced to /CAS Read command hold referenced to /RAS Write command hold time Write command hold referenced to /RAS Write command pulse width Write command to /RAS lead time Write command to /CAS lead time Data-in set-up time Data-in hold time Refresh period Write command set-up time /CAS setup time (C-B-R refresh) /CAS hold time (C-B-R refresh) /RAS precharge to /CAS hold time NOTES tRAH tASC tRAL tRCS tRCH tRRH tWCH tWCR tWP tRWL tCWL tDS tDH tREF tWCS tCSR tCHR tRPC 0 5 10 5 10 0 25 0 0 0 10 50 10 13 8 0 8 64 0 5 10 5 10 0 30 0 0 0 10 55 10 15 10 0 10
HMD32M32M16G
ns ns ns ns ns ns ns ns ns ns ns ns ns 64 ns ns ns ns ns
1.An initial pause of 200s is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles
before proper device operation is achieved.
2.VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
3.Measured with a load equivalent to 2TTL loads and 100pF 4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD
is greater than the specified tRCD(max) limit, then access time is controlled exclusively by t CAC.
5.Assumes that tRCD tRCD(max)
6. tAR, tWCR, tDHR are referenced to tRAD(max) 7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V OH or VOL. 8. tWCS, tRWD, tCWD anf tAWD are non restrictive operating parameter. They are included in the data sheet as electrical characteristic only. If t WCS tWCS(min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. 9. Either tRCH or tRRH must be satisfied for a read cycle. 10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in readwrite cycles. 11. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit. then access time is controlled by tAA.
AC CHARACTERISTICS
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( 0 C TA 70oC , Vcc = 5V10%)
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o
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-5 PARAMETER Hyper page mode cycle time /CAS precharge time (Hyper page cycle) /RAS pulse width (Hyper page cycle) /RAS hold time from /CAS precharge /W to RAS precharge time (C-B-R refresh) /W to RAS hold time (C-B-R refresh) Output data hold time Output buffer turn off delay from /RAS Output buffer turn off delay from W /W to data delay /W puls width NOTES SYMBOL MIN tHPC tCP tRASP tRHCP tWRP tWRH tDOH tREZ tWEZ tWED tWPE 20 8 50 30 10 10 5 3 3 15 5 13 13 200K MAX MIN 25 10 60 35 10 10 5 3 3 15 5 -6
HMD32M32M16G
UNIT MAX ns ns 200K ns ns ns ns ns 15 15 ns ns ns ns
NOTE 11
6,12 6
1. An initial pause of 200us is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles before proper device operation is achieved. 2. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 1 TTL loads and 100pF. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCD tRCD(max). 6. This parameter defines the time at which the output achieves the open circuit and is not referenced for V OH or VOL. 7. tWCS is non-restrictive operating parameter. It is included in the data sheet as electrical characteristics only. If tWCS tWCS(min), the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameters are referenced to the /CAS leading edge in early write cycles. 10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as reference point only. If tRAD is greater than the specified tRAD(max) limit access time is controlled by tAA. 11. tASC 6ns, Assume t T=2.0ns. 12. If /RAS goes high before /CAS high going, the open circuit condition of the output is achieved by /CAS high going. If /CAS goes high before /RAS high going , the open circuit condition of the output is achieved by /RAS going. .
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PACKAGING INFORMATION
HMD32M32M16G
2.54 mm 0.25 mm MAX MIN
Gold: 1.040.10 mm 1.27 mm Solder: 0.9140.10 mm
1.270.08mm
(Solder & Gold Plating)
ORDERING INFORMATION
Part Number Density Org. Package Component Number 16EA 16EA Vcc MODE SPEED
HMD32M32M16G-5 HMD32M32M16G-6
128Byte 128Byte
x 32 x 32
72 Pin-SIMM 72 Pin-SIMM
5V 5V
FPM FPM
50ns 60ns
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